The present invention is generally directed to electronic design automation (EDA) for creating integrated circuit (IC) products, such as, for example, system on chip (SOC) IC products and the like. More specifically, the present invention is directed to providing a structurally aware timing model to representatively model operation of a circuit design. Such timing model allows for incorporation as a black box or functional block into an overarching hierarchical circuit design.
While circuit design modeling systems and methods are generally known, such heretofore known systems and methods are encumbered by numerous deficiencies, not the least of which are the inability to accurately perform sign off, pessimism reduction, optimization, and verification of a hierarchical system design incorporating a timing model with obscured structural features therein. While in the past, a timing model with an operational timing characteristic thereof had been provided and integrated into a hierarchical circuit design, substantial problems remained with performing adequate timing analysis and other such associated tasks on the hierarchical system design incorporating the timing model. One illustrative timing verification step encountering problems with such abstracted timing model is a static timing analysis (STA). Aggravating the problem, timing analyses generally include a predetermined level of pessimism incorporated therein to ensure that the circuit design will not fail due to silicon, logic, or timing issues therein.
Such pessimism is added to the timing report of the circuit design to compensate for the obscured timing model and generally requires remedial changes to the design which leads to degraded power/performance/area (PPA) or lowering the clock speed of the finished IC product to ensure proper functionality. Pessimism introduced during timing analysis of the circuit design greatly limits the ability of circuit designers to realize power efficiency, minimized area, and optimal performance at maximized operating frequencies. While the pessimism does guard against very serious silicon flaws, it tends to cause the embodied circuit design to be less than optimal. In a timing analysis, it is seen that the timing analyzer module will generally err on the side of conservatism or pessimism i.e. even finding a timing violation where one may not actually exist.
Once a circuit design has been placed and routed, the static timing analysis (STA) is generally executed upon the circuit design to determine timing violations according to an arrival time at a certain point across a signal path relative to a required time for the given signal at that point in the circuit design. Such required time constraint may be mandated implicitly, such as by necessary operation of sequential features of registers, flip-flops, and other sequentially operated elements. Another type of constraint defining required arrival times are the explicit definitions of constraints upon certain features of the circuit design. For example, a circuit designer may constrain the circuit design to ensure that, for example, a certain signal reaches a certain point within a certain time. If a timing violation does exist but is not caught due to the timing analyzer portion being too generous or optimistic, such missed violation may lead to a defective and non-functional IC product. For this reason, it is common practice to build in a certain amount of pessimism at each stage of the design, so that sufficient margin is allowed for even a worst-case signal arrival to fall within a range of acceptable times for the circuit design.
Therefore, following formal verification or sign-off, a large amount of pessimism has been aggregated throughout each step of the circuit design to generate a timing report for the circuit design cataloging the operational timing characteristics across a number of signal paths thereof. Therefore, it is standard in the industry following a timing analysis, or sign off, to reduce or remove, unnecessary pessimism without introducing optimism into the timing report to arrive at realistic timing characteristics.
A timing report generally lists a number of signal paths including a starting point and an ending point such as an input 1 to output 2 and the like. Each of the signal paths are defined by a beginning point and an ending point, generally having at least one operational timing characteristic described, such as arrival time, required time, and a slack time. Slack time generally reflects the required time minus the arrival time, and indicates whether a signal arrives on time, early, or late. In the case of a negative slack time where the required signal arrived at a time later than the required time, the signal path may be determined to be violating a timing constraint (either implicit or explicitly defined). While there may be a wide range of possible violations (for example, 10 to 10,000 or more detected timing violations) on a given circuit design, it may be seen that a certain number n of the possible timing violations may be due solely to an overly pessimistic analysis maintained by the timing analysis engine. Thus, some portion n of the great many timing violations possible may be safely removed by reducing or removing an amount of pessimism in those instances—though this runs the risk of introducing fatal flaws to the circuit design. A number of measures have been proposed for safely addressing this removal of pessimism in the timing report of the circuit design.
Some measures of cited include a common path pessimism removal (CPPR), execution of a follow-up analysis, an on-chip variation (OCV) execution, and a statistical timing analysis (SSTA), and the like.
As an example, On Chip Variation (OCV) generally attempts to account for physical variations in the embodied circuit design across a physical semiconductor substrate. Such irregularities may come about due to a varying dopant concentration, divergent NMOS and PMOS operational timing characteristics, localized temperature hot-spots, or voltage irregularities throughout the circuit design. In OCV, a single derating factor is used to remove pessimism and is applied in blanket-fashion. For example, a timing path having a specific arrival time of, for example, 1000 picoseconds may be reduced by a derating factor of 0.8 OCV to be attributed an arrival time of 800 picoseconds. If the 800 picoseconds (as opposed to the 1000 picoseconds) arrival time is found to not be violating the required time, then this signal path would be removed from the list of violating signal paths. As another example, a derating factor of 1.2 may be applied resulting in a 1200 picoseconds arrival time which incorporates 200 picoseconds of pessimism introduced by the derate factor of 1.2.
Generally, for each timing violation encountered, additional circuit elements must be added to the circuit design, removed, resized, exchanged for other stronger/weaker devices, or the clock frequency of the circuit design must be degraded to allow for proper operation of the circuit product. Such addition, resizing, and degradation of processing speed certainly affect the power, performance, and area characteristics of the circuit design.
Traditional sign-off and placement and routing (P&R) optimizer systems and methods are sub-optimal. The presence of detected timing violations conventionally resulted in an unacceptable amount of repeated iterative loops between the sign-off module and the optimization placement and routing module. Indeed, such looping may have taken days, hours, or weeks depending on the size of the circuit design and the number of timing violations determined therein. As circuit designs exceeding 200+ million instances are not uncommon, the problem is aggravated unceasingly. Worse yet, the fixing of a particular timing violation such as by adding a gate to remedy one timing violation, may introduce, for example, 100 or 1000 new timing violations which must each be iteratively addressed, themselves perhaps spawning 1000 new violations in a Hydra-like loop. In such manner, the signing off of a circuit design is often a very labor, time, capital, memory, and processing-resource intensive task.
Such deficiencies have heretofore hindered efforts to minimize fabricated integrated circuit product cost, time-to-market, power requirements, and substrate area, while maximizing performance.
There is therefore a need for a system and method for generation and use of a structurally-aware timing model of a circuit design while protecting the implementation details thereof from misappropriation.